The present invention relates to a timer circuit, and more specifically, to a timer circuit for an integrated circuit arrangement.
It is customary to develop a unique control system for each specific model of an apparatus. For example, in the electronic postage meter area, each postage meter model has a micro-controller system specifically designed for controlling the function set of that electronic postage meter model. The micro-controller system is customarily comprised of a microprocessor in bus communication with a number of memory units and an applications specific integrated circuit (ASIC). It is now considered advantageous to develop a single micro-controller for a plurality of meter models which will offer the advantages of allowing one micro-controller to be utilized in a number of meters resulting in less variations in meter design and better design control for the manufacturer.
One of the principle obstacles is that each microprocessor control system is constrained to performance limitation of specific integrated circuit components, such as, the write rate to non-volatile memory units, baud rate to peripheral units. As a result, it is conventional to provide the necessary circuit timers with fixed mode operation, i.e., continuous or one-shot, for a specific control operation. It is recognized that because the timer is so constrained within the control circuit that only like timed events may be logically connected to that timer.